This invention relates generally to electronic circuits, and more particularly, to RF power amplifier circuits.
Power amplifiers, such as power amplifiers used in base stations of cellular communication systems, often operate at output power levels much lower than peak power. Unfortunately, the back-off power level reduces the efficiency of the power amplifier in the transmitter. In a conventional amplifier there is a direct relationship between efficiency and the input drive level. Therefore, high efficiency (DC to RF conversion efficiency) is often not obtained until the RF input power level becomes sufficiently high to drive the amplifier into compression or saturation. In multi-carrier communication systems where it is desirable for an amplifier to remain as linear as possible, this region of high efficiency cannot be used.
A power amplifier circuit design that provides improved efficiency in back-off power levels is the Doherty amplifier circuit, which combines power from a main or carrier amplifier and from an auxiliary or peak amplifier. See, W. H. Doherty, “A New High-Efficiency Power Amplifier for Modulated Waves,” Proc. IRE Vol. 24, No. 9, pp. 1163-1182, 1936. A conventional Doherty circuit 20 is illustrated in FIG. 1A. As shown therein, an input signal applied to an input terminal 21 is split by a splitter 22. A main or carrier amplifier 23 and a peak amplifier 26, which receive the input signal from the splitter 22, are designed to deliver maximum power with increased efficiency to a load R. The carrier amplifier 23 receives the input signal directly from the splitter 22, while the peak amplifier 26 receives the input signal through a quarter wave (90°) transformer 25. The output of the carrier amplifier 23 passes through another quarter wave (90°) transformer 24, and is combined with the output of the peak amplifier 26 at a combining node 27. Accordingly, the outputs of the carrier amplifier 23 and the peak amplifier 26 are not isolated from one another. Thus, when the peak amplifier 26 turns on, the apparent load presented to the carrier amplifier 23 changes.
The carrier amplifier 23 is biased as a normal Class B amplifier, while the peak amplifier 26 is designed to only amplify signals which exceed some minimum threshold. For an LDMOS power transistor, this can be accomplished by DC biasing the transistor below its pinch-off voltage, for operation similar to Class C. The outputs of the two amplifiers are connected by a quarter-wave transmission line 24 of characteristic impedance R, and a load of one-half of the optimum load R is attached to the output of the peak amplifier 26. The RF input power is divided equally with a quarter-wave delay 25 at the input to the peak amplifier 26, thus assuring that the output power of the two amplifiers at the load R/2 28 will be in phase.
The Doherty amplifier circuit achieves high efficiency prior to compression by operating the Class B carrier amplifier 23 into an apparent load impedance two times larger than its optimum load. (Before the peak amplifier 26 becomes active, the apparent load impedance presented to the carrier amplifier 23 is 2R due to the presence of quarter wave transformer 24.) Thus, the carrier amplifier 23 compresses and reaches peak efficiency at half of its maximum power. The second or peak amplifier becomes active only during the peaks of the input signal. When the peak amplifier is active, the load impedance apparent at the output of the carrier amplifier 23 is reduced. High efficiency can again be achieved when the peak amplifier 26 outputs its full power. Thus, the carrier amplifier 23 is kept on the verge of saturation for a 6 dB range of output power and near-peak efficiency may be maintained.
When the input RF power into the Doherty amplifier circuit is not sufficient to turn on the peak amplifier 26, substantially all of the output power is supplied by the carrier amplifier 23. When the peak amplifier 26 is off, its output impedance is very high and the output power of the carrier amplifier 23 is essentially all delivered to the load R/2. As discussed above, the load actually presented to the carrier amplifier across the quarter-wave transformer 24 is 2R. The device current is therefore one-half of what is delivered at maximum power while the voltage is saturated. This results in the device delivering half its maximum output power. Since both the RF and DC components of the current are half their peak values, the efficiency will be at its maximum with half of the maximum output power of the carrier amplifier being supplied to the load with maximum linear efficiency.
When sufficient input RF power is provided to allow the peak amplifier 26 to become saturated, the two parallel amplifiers are evenly delivering maximum output power to the load R/2. The load apparent to each amplifier is then the optimum load R, and the load at both ends of the quarter-wave transformer 24 will remain at R. The peak amplifier 26 is designed to begin operation when the carrier amplifier 23 just begins to saturate, which may provide the highest linear efficiency. As the input RF drive is further increased, the peak amplifier begins to turn on and deliver output power to the load. The additional current supplied by the peak amplifier 26 has the effect of increasing the load impedance at the output of the quarter-wave transformer 24. The effective change at the carrier amplifier end of the transformer 24 will be a reduction in the apparent load impedance and enabling the carrier amplifier 23 to deliver more power while its voltage remains saturated. The efficiency between the limits will fall off only slightly from the maximum since the duty factor of the peak amplifier is relatively low.
Some efforts have been made to extend the range over which the output power and near-peak efficiency of a Doherty amplifier can be maintained. For example, U.S. Pat. No. 6,791,417, entitled “N-Way RF Power Amplifier Circuit With Increased Back-Off Capability And Power Added Efficiency Using Selected Phase Lengths And Output Impedances,” discloses a Doherty amplifier with multiple peak amplifiers. A four-way Doherty amplifier circuit 30 is illustrated in FIG. 1B. As shown therein, a carrier amplifier 33 and the three peak amplifiers 36A-C are provided, with the peak amplifiers 36A-C connected through 90° transformers 35A-C to an output load 38. A single 90° transformer 34 connects a four-way splitter 32 to the carrier amplifier 34. By setting the DC bias on each of the peak amplifiers 36A-C to appropriate values, the added peak amplifiers allow the Doherty action to be extended. The outputs of carrier amplifier 33 and peak amplifiers 36A-C are combined at combining node 37. For each peak amplifier that is added above the first, there will be a corresponding increase of 6 dB in the power range over which the peak efficiency will be maintained. Some limitation in efficiency will result due to the finite loss in the N-way splitter. The four-way amplifier extends the range of efficient power to a theoretical value of 18 dB. The four-way configuration can provide an overall power increase of 3 dBm compared to a two-way Doherty amplifier circuit. Thus, a 120 watt peak amplifier can be provided by a four-way Doherty arrangement with each path (a carrier and three peak amplifiers) utilizing 30 watt transistors.
Although the use of separate carrier and peak amplifiers in Doherty amplifiers can provide increased efficiency, they may have an insufficient power range for some applications. Moreover, the circuit components, including the splitters, quarter wave transformers, and combiners, may restrict the amplifier's net bandwidth, efficiency, and/or gain flatness over a desired range of power levels and/or operating frequencies.